1. Field of the Invention
The present invention relates to semiconductor device manufacturing, and more particularly, maintaining equivalency between a logical design and a physical design of an integrated circuit.
2. Description of the Related Art
Integrated circuits (IC), such as application specific integrated circuits (ASIC), are typically designed using computer-aided design (CAD) tools using a hardware description language (HDL) that allow the designer to specify, in software, the logical operation of the chip. One such example of a hardware description language is Verilog.
Known design processes include several steps. First, a designer writes a software program describing the flow of signals in the chip and the logical operations performed on those signals. In Verilog, for example, such a program is written at the Register Transfer Level (RTL). Once the designer has programmed the operation of the logic circuit, the program is simulated and, if acceptable, synthesized into a corresponding collection of standard cells. Standard cells are components, such as logic gates, latches, decoders, and various other components, that exist in a library accessible by a synthesis tool. The synthesis step is typically an automated process in which the synthesis tool determines the appropriate standard cells and interconnections between standard cells to realize a circuit that satisfies the RTL model.
Conventional design flows derive a schematic from a reference RTL, then a layout from the schematic, to assist in maintaining functional and physical correctness. In an aggressive integration methodology, the modification of logic represented by the layout due to placement, route topologies, and clock loading constraints can create a mismatch between RTL and the layout. Hence, no reference schematic exists. To optimize performance, current integrated circuit design approaches allow the designer to specify the logic gate cell sizes for timing purposes, to cluster cells dynamically based on placement constraints, to balance clock loads, and to order scan chains. However, these approaches can create a vast difference between the RTL and corresponding layout, and create a need to back-annotate information into RTL. What is needed is a way to maintain equivalency between the physical layout and the reference RTL of the design.